In some multi-processor computer systems, there is sometimes a need to synchronize the processors. For example, a multi-processor computer system (MPCS) may periodically execute a diagnostic program to ensure that the MPCS is functioning properly. A part of the diagnostic may involve testing the memory caches associated with the MPCS's multiple processors. During memory cache testing for a given processor, it is may be required that the cache state of that processor does not change during the memory cache test. Unless the processors are synchronized prior to the memory cache test, the cache state of the memory cache associated with a given processor may unexpectedly change if another processor accesses main memory and, for example, writes to the data being cached by the given processor.
To facilitate discussion, considering the diagram of FIGS. 1A and 1B. The diagrams of FIG. 1A and FIG. 1B may represent different instantiations of a single diagnostic program being executed by a processor A and a processor B respectively, for example. In FIG. 1A, instructions of the diagnostic program are represented by the horizontal line between START (102) and END (104), with the shaded portion CACHE TEST (106) representing the cache test instructions. During the execution of CACHE TEST (106) instructions by a given processor A, it is required that the cache state of processor A be unchanged.
In FIG. 1B, instructions of the diagnostic program is again represented by the horizontal line between START (112) and END (114), with the shaded portion CACHE TEST (116) representing the cache test instructions. During the execution of CACHE TEST (116) by a given processor B, it is required that the cache state of processor B also be unchanged.
Suppose that the processors are not synchronized prior to starting their respective cache tests. If processor A is currently executing an instruction 108 within CACHE TEST (106), and processor B is currently executing an instruction 118 outside of CACHE TEST (116), the cache state of processor A may change due to memory access by processor B. This is because some memory controller may flush the caches of all processors currently caching a data item if one of the processors accesses that data item in main memory for writing, for example. When this happens, the diagnostic test being executed for processor A may provide an incorrect result, such as indicating a failure with its cache even though the cache may, in reality, be error-free.